View LH5P1632_394468.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LH5P1632
FEATURES * 32,768 x 16 bit organization * Access time: 80/150 ns (MAX.) * Cycle time: 140/210 ns (MIN.) * Single +5 V power supply * Power consumption (MAX.): Operating: 467.5/327.5 mW Standby: 16.5 mW * TTL compatible I/O * 256 refresh cycles/4 ms (MAX.) * Available for auto-refresh mode * Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP DESCRIPTION
CMOS 512K (32K x 16) Pseudo-Static RAM
PIN CONNECTIONS
40-PIN DIP 40-PIN SOP GND A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC UWR LWR A10 A11 A12 A13 A14 UOE/TEST1 LOE/RFSH CE I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 VCC
5P1632-1
TOP VIEW
The LH5P1632 is a 512K-bit Pseudo-Static RAM organized as 32,768 x 16 bits. It is fabricated using silicon-gate CMOS process technology.
Figure 1. Pin Connections for DIP and SOP Packages
1
LH5P1632
CMOS 512K (32K x 16) Pseudo-Static RAM
21 VCC 20 GND A0 11 A1 10 A2 9 A3 8 A4 7 A5 6 A6 5 A7 4 A8 3 A9 2 A10 37 A11 36 A12 35 A13 34 A14 33
VBB GENERATOR
40 VCC 1 GND
A8 - A14 COLUMN ADDRESS BUFFER
COLUMN DECODER
A0 - A7
ROW ADDRESS BUFFER
SENSE AMPS
I/O SELECTOR
DATA IN BUFFER
12 I/O1 13 14 15 16 I/O2 I/O3 I/O4
REFRESH ADDRESS COUNTER
EXT/INT ADDRESS MUX
ROW DECODER
MEMORY ARRAY
DATA OUT BUFFER
I/O5 17 I/O6 18 I/O7 19 I/O8
DATA IN BUFFER CE 30 CLOCK GENERATOR
23 24 25 26
22 I/O9 I/O10 I/O11 I/O12
DATA OUT BUFFER REFRESH CONTROLLER
I/O13 27 I/O14 28 I/O15 29 I/O16
LOE/ 31 RFSH UOE/ TEST1 32 LWR 38 LWR 39
5P1632-2
Figure 2. LH5P1632 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A14 LWR, UWR LOE/RFSH, UOE CE
Address input Write enable Output enable/Refresh input Chip enable input
I/O1 - I/O16 VCC GND
Data input/output Power Supply Ground
2
CMOS 512K (32K x 16) Pseudo-Static RAM
LH5P1632
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Applied voltage on all pins Output short circuit current Power dissipation Operating temperature Storage temperature
VT IO PD Topr Tstg
-1.0 to +7.0 50 600 0 to +70 -65 to +150
V mA mW C C
1
NOTE: 1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Supply voltage Input voltage
VCC GND VIH VIL
4.5 0 2.4 -0.3
5.0 0
5.5 0 VCC + 0.3 0.8
V V V V 1
NOTE: 1. VIL (MIN.) = -1.0 V when the pulse width is less than 20 ns.
CAPACITANCE (TA = 0 to +70C, f = 1 MHz, VCC = 5.0 V 10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
A0 - A14 Input capacitance LWR, UWR CE LOE/RFSH, UOE Input/Output capacitance I/O1 - I/O16
CIN1 CIN2 CIN3 CIN4 COUT1
8 5 5 5 10
pF pF pF pF pF
DC CHARACTERISTICS (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Average supply current in normal operation tRC = t RC (MIN) Supply current in standby mode Average supply current in CPU internal cycle (LWR = UWR = LOE/RFSH = UOE = V IH) Input leakage current I/O leakage current Output HIGH voltage Output LOW voltage
NOTES: 1. Specified values are with outputs open. 2. I CC1 and ICC3 depend on the cycle time. 3. CE = High, LOE/RFSH = High.
LH5P1632-80 ICC1 ICC2 LH5P1632-80 ICC3 LH5P1632-15 0 V VIN 6.5 V, 0 V except on test pins 0 V VOUT VCC + 0.3 V, Outputs in high-impedance state IOUT = -1.0 mA IOUT = 4.0 mA -10 -10 2.4 LH5P1632-15
85 mA 65 3.0 85 mA 1, 2 mA 1, 3 1, 2
ILI ILO VOH V OL
10 10
A A V
0.4
V
3
LH5P1632
CMOS 512K (32K x 16) Pseudo-Static RAM
AC CHARACTERISTICS 1, 2, 3 (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL MIN. -80 ns MAX. -150 ns MIN. MAX. UNIT NOTE
READ OR WRITE CYCLE Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time Address setup time Address hold time Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z OE to output in Low-Z OE setup time for WR Output disable time from CE Output disable time from OE Output disable time from WR OE setup time OE hold time OE lead time Write command pulse width Write command setup time Write command hold time Data setup time from WR Data setup time from CE Data hold time from WR Data hold time from CE Transition time (rise and fall) Refresh time interval Auto refresh cycle time Refresh delay time from CE Refresh pulse width (Auto Refresh) Refresh precharge time (Auto Refresh) CE delay time from Refresh active (Auto Refresh) tRC tRMW tCE tP tAS tAH tRCS tRCH tCEA tOEA tCLZ tOLZ tOSW tCHZ tOHZ tWHZ tOES tOEH tOEL tWCP tWCS tWCH tDSW tDSC tDHW tDHC tT tREF tFC tRFD tFAP tFP tFCE REFRESH CYCLE 140 50 30 40 160 8,000 10 0 0 0 0 0 10 0 10 60 60 60 30 30 0 0 3 35 4 190 60 80 30 225 8,000 25 25 25 140 205 80 50 0 20 0 0 80 30 10 0 0 0 0 0 10 0 10 85 85 85 50 50 0 0 3 35 4 35 35 35 10,000 210 280 150 60 0 30 0 0 150 70 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns 5 5 4 4
NOTES: 1. In order to initialize the circuit, CE and OEL/RFSH should be kept VIH for 200 s after power on and followed by at least 8 dummy cycles. 2. AC characteristics shall be tested with t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Address is latched at the negative edge of CE. 5. Measured with a load equivalent to 2TTL + 100 pF. 6. Data for the lower byte (I/O1 to I/O 8) is latched at the positive edge of LWR or the positive edge of CE. Data for the upper byte (I/O9 to I/O 16) is latched at the positive edge of UWR or the positive edge of CE.
INPUT
2.4 V 0.8 V
2.6 V 0.6 V 2.2 V 0.8 V
OUTPUT
5P1632-9
Figure 3. AC Characteristics
4
CMOS 512K (32K x 16) Pseudo-Static RAM
LH5P1632
TRUTH TABLE
INPUT CE UOE LOE/RFSH UWR LWR OUTPUT I/O9 - I/O16 I/O1 - I/O8 MODE UPPER BYTE LOWER BYTE NOTE
H L L L L L L L L L H
D L H L H D D H D L D
D L L H H D H D L D
D H H H H L L H L H D
D H H H H L H L H L D
High-Z DOUT High-Z DOUT High-Z DIN DIN High-Z DIN DOUT High-Z
High-Z DOUT DOUT High-Z High-Z DIN High-Z DIN DOUT DIN High-Z Read
Standby Read Read CE only refresh CE only refresh Write CE only refresh Write Read Write Auto Refresh Inhibit Inhibit CE only refresh Read CE only refresh Write Write CE only refresh Write Read
NOTES: D = Don't care. High-Z = High impedance.
tRC tP VIH VIL tAS VIH VIL tAH tCE tP
CE
A0 - A14
ADDRESS INPUT tOEH tOEL tOES
LOE/RFSH VIH VIL UOE tRCS LWR VIH UWR VIL tCEA tOEA V I/O1 - I/O16 VOH OL tOLZ tCLZ
5P1632-3
tRCH
tCHZ tOHZ
VALID-DATA OUTPUT
Figure 4. Read Cycle
5
LH5P1632
CMOS 512K (32K x 16) Pseudo-Static RAM
tRC tP VIH CE VIL tAS VIH A0 - A14 VIL tOES V LOE/RFSH IH VIL UOE tWCH tWCS tWCP LWR VIH UWR VIL tDSW tDSC VIH VIL tDHW tDHC tAH tCE tP
ADDRESS INPUT tOEH
I/O1 - I/O16
VALID-DATA INPUT
5P1632-4
Figure 5. Write Cycle
6
CMOS 512K (32K x 16) Pseudo-Static RAM
LH5P1632
tRMW tP VIH VIL tAS V A0 - A14 VIH IL tAH tP
CE
ADDRESS INPUT tOEH
LOE/RFSH VIH VIL UOE tRCS tOSW tWCS tWCP
LWR VIH UWR VIL tDSW tDSC VIH VIL tCEA I/O1 - I/O16 tOEA VOH VOL tOLZ tCLZ tWHZ tOHZ tDHW tDHC
VALID-DATA INPUT
VALID-DATA OUTPUT
5P1632-5
Figure 6. Read-Write Cycle
7
LH5P1632
CMOS 512K (32K x 16) Pseudo-Static RAM
tRC tP VIH VIL tAS V A0 - A7 VIH IL tOES LOE/RFSH VIH VIL UOE tRCS LWR UWR VIH VIL tRCH tAH tCE tP
CE
ADDRESS INPUT tOEH
I/O1 - I/O16 VOH VOL NOTE: A8 - A14 = Don't Care
HIGH - Z
5P1632-6
Figure 7. CE Only Refresh Cycle
V CE VIH IL tRFD tFAP V LOE/RFSH VIH IL tFC tFP tFAP tFCE
I/O1 - I/O16 VOH VOL NOTE: A0 - A14, LWR, UWR, UOE = Don't Care
HIGH - Z
5P1632-7
Figure 8. Auto Refresh Cycle
8
CMOS 512K (32K x 16) Pseudo-Static RAM
LH5P1632
PACKAGE DIAGRAMS
40DIP (DIP040-P-0600)
40 21
DETAIL
13.45 [0.530] 12.95 [0.510]
1 52.30 [2.059] 51.70 [2.035]
20
0 TO 15 0.30 [0.012] 0.20 [0.008]
4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
40DIP
40-pin, 600-mil DIP
40SOP (SOP040-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 21
0.50 [0.020] 0.30 [0.012]
40
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 26.50 [1.043] 26.10 [1.028]
20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
40SOP
40-pin, 525-mil SOP
9
LH5P1632
CMOS 512K (32K x 16) Pseudo-Static RAM
ORDERING INFORMATION
LH5P1632 Device Type X Package - ## Speed 15 150 Access Time (ns) 80 80 D 40-pin, 600-mil DIP (DIP040-P-0600) N 40-pin, 525-mil SOP (SOP040-P-0525) CMOS 512K (32K x 16) Pseudo-Static RAM Example: LH5P1632N-80 (CMOS 512K (32K x 16) Pseudo-Static RAM, 80 ns, 40-pin, 525-mil SOP)
5P1632-8
10

▲Up To Search▲

Price & Availability of LH5P1632

	To Download LH5P1632 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .